Approximate Speculative Adder for Low Power VLSI Architectures
C. Srinivasa Murthy1, K. Tarakeswara Rao2, K Sridevi3
1C Srinivasa Murthy, Research Scholar, GITAM Institute of Technology GITAM Deemed to be University, Vishakhapatnam (Andhra Pradesh), India.
2K. Tarakeswara Rao, Research Scholar, GITAM Institute of Technology GITAM Deemed to be University, Vishakhapatnam (Andhra Pradesh), India.
3Dr. K. Sridevi, Associate Professor, GITAM Institute of Technology, GITAM Deemed to be University, Vishakhapatnam (Andhra Pradesh), India.
Manuscript received on 22 November 2019 | Revised Manuscript received on 10 December 2019 | Manuscript Published on 30 December 2019 | PP: 32-34 | Volume-9 Issue-2S3 December 2019 | Retrieval Number: B10081292S319/2019©BEIESP | DOI: 10.35940/ijitee.B1008.1292S319
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open-access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Approximate Speculative Adder (ASA) for low energy dissipation is proposed in this paper. To enhance the speed of operation pipelining technique is been employed and also to lower the critical path delay utilization of logic gates are also reduced. The structure employs carry look ahead logic for adder implementation. Different configurations have been examined for area and speed. The prime aim lies for lowering the dissipative energy. Also clock skew technique is employed to save the dynamic power consumption. The structure is been analyzed with FPGA and also realized with ASIC. Analysis of results states about the performance of ASA can operate at higher speed than the existing structures. The structure absorbs 5.109 mm2 of chip space. The proposed Approximate Speculative Adder consumes 52.75% of power.
Keywords: Approximate Speculative adder, Carry Look Ahead Adder, Pipelining.
Scope of the Article: Low-power design