Research on Power Efficient Clock Distribution Schemes for Switching Converters
S. Karunakaran1, R RaniHemamalini2
1S. Karunakaran*, Research Scholar, Bharath university & Associate professor, Saveetha Enginering college, Chennai, Tamil Nadu, India
2Dr R RaniHemamalini, Professor & Head, ECE, St. Peters College of Engg. & Tech. Chennai, Tamil Nadu, India.
Manuscript received on October 12, 2019. | Revised Manuscript received on 22 October, 2019. | Manuscript published on November 10, 2019. | PP: 2953-2957 | Volume-9 Issue-1, November 2019. | Retrieval Number: A9114119119/2019©BEIESP | DOI: 10.35940/ijitee.A9114.119119
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Trends in VLSI technology represents bottleneck for the future high performance computing architectures as the ratio of the power pins to the total package pins keeps on increasing. A viable solution to this is bottleneck is to have final power consumption on-chip. Switched Capacitor DC-DC Converters are the most preferred for on-chip power conversion. However, as the number of power conversion modules increases and they get distributed across the chip area, clock distribution for the switched capacitor converters becomes a non-trivial task and the increased interconnect lengths cause clock degradation and power dissipation. This paper presents a power efficient signaling topology for driving the clocks to higher interconnect lengths.
Keywords: VLSI, Switched Capacitor Converters, Interconnects
Scope of the Article: VLSI Algorithms