Low Voltage CMOS Power Amplifier with Integrated Capacitive Harmonic Termination
Sureshkumar Subramian1, Jagadheswaran Rajendran2, Arvind Singh Rawat3, Sofiyah Sal Hamid4
1Sureshkumar Subramian*, Collaborative Microelectronic Design Excellence Centre (CEDEC), School of Electrical and Electronic Engineering, Universiti Sains Malaysia.
2Jagadheswaran Rajendran, Collaborative Microelectronic Design Excellence Centre (CEDEC), School of Electrical and Electronic Engineering, Universiti Sains Malaysia.
3Sofiyah Sal Hamid, Collaborative Microelectronic Design Excellence Centre (CEDEC), School of Electrical and Electronic Engineering, Universiti Sains Malaysia.
4Arvind Singh Rawat. Assistant Professor Department of Electronics & Communication Engineering, Uttaranchal University, Dehradun.
Manuscript received on November 14, 2019. | Revised Manuscript received on 22 November, 2019. | Manuscript published on December 10, 2019. | PP: 108-111 | Volume-9 Issue-2, December 2019. | Retrieval Number: A5021119119/2019©BEIESP | DOI: 10.35940/ijitee.A5021.129219
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper presents a novel design methodology to improve the power added efficiency (PAE) for a CMOS power amplifier (PA), qualifying it for low voltage mobile wireless communications such as the NB-IoT. The capacitive harmonic termination (CHT) integrated at the output of the main stage PA to minimise the effect of the second harmonic distortion in order to improve the PAE. The CHT PA able to deliver a PAE of 40% at drain voltage of 3.3 V from 1.9 GHz – 2.1 GHz. The corresponding power gain is 14 dB for 200 MHz bandwidth. The achieved third-order intercept point (OIP3) is 33 dBm, which serves as a proof that the CHT technique has a minimal trade-off to the linearity performance of the PA.
Keywords: Power Amplifier (PA), CMOS, Capacitive Harmonic Termination (CHT), Power Added Efficiency (PAE)
Scope of the Article: Nanometer-Scale Integrated Circuits