Performance Analysis of Non-Identical Master Slave Flip Flops at 65nm Node
Urvashi Chopara1, Alok Kumar Mishra2, D. Vaithiyanathan3
1Urvashi Chopra, PG Student, Department of Electronics and Communication Engineering, National Institute of Technology, (Delhi), India.
2Alok Kumar Mishra, Ph.D Scholar, Department of Electronics and Communication Engineering, National Institute of Technology, (Delhi), India.
3D. Vaithiyanathan, Assistant Professor, Department of Electronics and Communication Engineering, National Institute of Technology, (Delhi), India.
Manuscript received on 22 November 2019 | Revised Manuscript received on 03 December 2019 | Manuscript Published on 14 December 2019 | PP: 18-21 | Volume-9 Issue-1S November 2019 | Retrieval Number: A10051191S19/2019©BEIESP | DOI: 10.35940/ijitee.A1005.1191S19
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open-access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper presents the performance analysis of the different master slave flip flop reported and comparison of their parameters such as power, area, delay setup time and hold time. To reduce the number of transistor count various logic structure mater slave design have been proposed that results reduction in total area of the flip flop. Advantage and disadvantage of the each flip flop has been discussed. Process corner analysis of all flip flop is also presented at supply voltage of 0.7 volts at 27°C temperature. Percentage reduction in power and speed of operation i.e. frequency are discussed.
Keywords: Transmission Gate, Auxiliary Transistor, Flip Flop, Switching Activity.
Scope of the Article: Measurement & Performance Analysis