Design of Test Pattern Generator for Testing Crosstalk Faults in TSVs
K. Praveen Kumar Reddy1, P. Rangarajan2
1K. Praveen Kumar Reddy, Department of EEE, RMD Engineering College, Kavaraipettai (Tamil Nadu), India.
2Dr. P. Rangarajan, Department of EEE, RMD Engineering College, India.
Manuscript received on 22 November 2019 | Revised Manuscript received on 03 December 2019 | Manuscript Published on 14 December 2019 | PP: 1-4 | Volume-9 Issue-1S November 2019 | Retrieval Number: A10011191S19/2019©BEIESP | DOI: 10.35940/ijitee.A1001.1191S19
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open-access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Design of Test pattern generator to test crosstalk faults in Through Silicon Vias (TSV) in three dimensional integrated circuits presented in this paper. A well-known test pattern generation model for testing crosstalk called as Maximum aggressor fault model is adopted in the design. The finite state machine diagram for design of TPG presented in reference [1] is modified and the complete design of TPG is discussed in this paper. Verilog HDL Simulation and synthesis results of the proposed Test pattern generator is discussed.
Keywords: Crosstalk, through Silicon Via, Test Pattern Generation. Maximum Aggressor Fault Model.
Scope of the Article: Microstrip Antenna Design and Application