8 Bit Second-Order Continuous-Time Band-Pass Sigma-Delta ADC
Nagaraj P1, Siva Yellampalli2
1Mr. Nagaraj P, Department of VLSI and Embedded System, VTU Extension Center, UTL Technologies Ltd., Bangalore (Karnataka), India.
2Dr. Siva Yellampalli, Department of VLSI and Embedded System, VTU Extension Center, UTL Technologies Ltd., Bangalore (Karnataka), India.
Manuscript received on 11 June 2013 | Revised Manuscript received on 17 June 2013 | Manuscript Published on 30 June 2013 | PP: 106-111 | Volume-3 Issue-1, June 2013 | Retrieval Number: A0899063113/13©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In this paper, a technique to design the 8 bit continuous-time band-pass Sigma-Delta converters for 70 MHz is presented. The conversion from discrete-time (z-domain) loop-filter transfer function into continuous-time (s-domain) is done by using Impulse-invariant-transformation. The transconductor-capacitor filter is used to implement continuous-time loop-filter. A latched-type comparator and a TSPC D Flip-flop are being used as the quantizer of the Sigma-Delta converter. The decimation filter is designed by a CIC Filter and an FIR filter of high-speed digital. A full adder cell and a TSPC D Flip-flop are used as basic building blocks of CIC Filter and FIR Filter. The 8 bit second-order continuous Sigma-Delta converter circuit has been implemented in Cadence using 180nm CMOS technology and the total power consumption is 57.9 mW. At a supply voltage of 3 V, the maximum SNDR is measured to be 35.13 dB, which corresponds to a resolution of 8 bits.
Keywords: Analog-to-digital Converter, Continuous Sigma-Delta ADC, Decimation Filter, Sigma-Delta modulator.
Scope of the Article: Digital Clone or Simulation