An Area Efficient, High Speed Novel VHDL Implementation of Linear Convolution of Two Finite Length Sequences using Vedic Mathematics
Madhura Tilak
Madhura Tilak, Electronics and Telecommunication Department Viva Institute of Technolgy Virar.
Manuscript received on 12 December 2012 | Revised Manuscript received on 21 December 2012 | Manuscript Published on 30 December 2012 | PP: 43-45 | Volume-2 Issue-1, December 2012 | Retrieval Number: A0368112112 /2012©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper presents a novel method of implementing linear convolution of two finite length sequences (N×N) in hardware using hardware description language (VHDL). The proposed method uses modified design approach by replacing the conventional multiplier by Vedic multiplier internally in the implementations. The proposed method is efficient in terms of computational speed, hardware resources and area significantly. The efficiency of the proposed algorithm is tested by simulations and comparisons with different design approaches using XILLINX software. The presented circuit consumes less power and has a delay of 17ns from input to output. The proposed circuit is also modular, expandable and regular which provides flexibility to form different number of bits.
Keywords: N×N, VHDL, XILLINX
Scope of the Article: Software Engineering Methodologies