FPGA Implementation of Polar Codes for Low Complexity Decoder for High Speed Applications
Raja Krishnamoorthy1, Manivel K2, A. Suresh Kumar3, C. Vairavel4
1Raja Krishnamoorthy, Professor, Department of Electronics and Communication Engineering, CMR Engineering College, Kandlakoya Village, Hyderabad, Telangana, India.
2Manivel K, Associate Professor, Department of Electronics and Communication Engineering, Mahendra Engineering, College, Namakkal, Tamilnadu, India.
3A. Suresh Kumar, Professor, School of Computing Science and Engineering, Galgotias University Delhi NCR, India.
4Mr. C. Vairavel, Assistant Professor, School of Computing Science and Engineering, Galgotias University, Delhi NCR, India.
Manuscript received on 28 August 2019. | Revised Manuscript received on 09 September 2019. | Manuscript published on 30 September 2019. | PP: 3281-3288 | Volume-8 Issue-11, September 2019. | Retrieval Number: K25350981119/2019©BEIESP | DOI: 10.35940/ijitee.K2535.0981119
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: An emerging error-detection and correcting technique developed in the recent years is Polar codes. The technique does not focus on randomization of the bits like other techniques does, but is based on the Shannon theory and channel polarization. This paper presents a successive cancellation (SC) algorithm based FPGA implementation of Polar codes. The implementation focuses on low complexity decoder for high speed applications. Software Simulation outcomes represent the execution to polar codes can outperform those are turbo or LDPC codes.
Keywords: FPGA Implementation of Polar Codes for Low Complexity Decoder for High Speed Applications
Scope of the Article: Analysis of Algorithms and Computational Complexity