Efficient Kernel Template AES Algorithm to Minimize Power Consumption and Maximize Security in Low Power Application
V. Nandan1, R. Gowri Shankar Rao2
1V.Nandan, Research Scholar, Department of Elect & Comm Engineering, Department of Elect & Comm Engineering, Veltech Rangarajan Dr.Sagunthala R& D, Inst. of science & Technology, Tamilnadu, India.
2R. Gowri Shankar Rao, Associate Professor, Department of Physics, Veltech Rangarajan Dr.Sagunthula R& D , Inst. of Science & Technology, Tamil Nadu, India,
Manuscript received on 21 August 2019. | Revised Manuscript received on 02 September 2019. | Manuscript published on 30 September 2019. | PP: 1645-1649 | Volume-8 Issue-11, September 2019. | Retrieval Number: K18920981119/2019©BEIESP | DOI: 10.35940/ijitee.K1892.0981119
Open Access | Ethics and Policies | Cite | Mendeley | Indexing and Abstracting
© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Cryptography involved in offering of secure data by generation of secret key through encryption process. At present, almost every applications require security scheme due to increased threats. Low power applications are limited to power sources where incorporation of attacks leads to certain challenges in terms of reduced throughput, data loss and increased power consumption hence it is necessary to adopt effective security scheme for low power application. Generally, in power circuits advanced encryption standard (AES) is incorporated which is defined as S-box. This substitution box is designed by 2 transformations (i.e) inversing the multiplication part in Galois field directed with modified affine transformation. The limitation of S-Box is more time and power consumption. In this paper, proposed a kernel based AES scheme for improving the performance of low power application. The proposed Kernal approach uses logic gate design with cipher text operation. The Kernel -AES technique is implemented in CMOS devices with 45nm standard cell technology. Results obtained for proposed Kernel-AES approach provides reduced power consumption rate of 28.5A which is comparatively less than conventional AES technique.
Keywords: Cryptography, XOR, Kernel, AES, Cipher text
Scope of the Article: Cryptography and Applied Mathematics