Design SSTL Based Energy Efficient Solar Charge Sensor on FPGA
Chandrashekhar Patel1, Sanjeev Kumar Sharma2, Abhay Saxena3
1Mr. Chandrashekhar Patel*, Lecturer, Department of Computer Science, Dev Sanskriti Vishwavidyalaya, Haridwar, India.
2Dr. Sanjeev Kumar Sharma, Professor, Department of Computer Science, Chitkara University, Chandigarh, India.
3Abhay Saxena, Dean (T.C&M), Department of Computer Science, Dev Sanskriti Vishwavidyalaya, Haridwar, India.
Manuscript received on September 16, 2019. | Revised Manuscript received on 24 September, 2019. | Manuscript published on October 10, 2019. | PP: 3114-3117 | Volume-8 Issue-12, October 2019. | Retrieval Number: K17280981119/2019©BEIESP | DOI: 10.35940/ijitee.K1728.1081219
Open Access | Ethics and Policies | Cite | Mendeley | Indexing and Abstracting
© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In this paper we have designed solar charge sensor which is used to make our battery efficient. Component is designed on Virtex 6 FPGA family and applied frequency scaling techniques. During the experiment, we have used different SSTL IO families and calculated total power consumption. In our work we have selected class I and class II from SSTL IO family. For the analysis we have used following range of frequency (20GHz, 40GHz, 60GHz and 80GHz). Firstly, we have worked with SSTL2_I and reduced total power consumption by 51.53%, in second experiment we have worked with SSTL2_I_DCI and reduced consumption of power by 47.18%. In third experiment we choose to work with SSTL2_II and reduced 51.58% in total power consumption. In fourth experiment we opted SSTL15 Io standard and downscale the total power consumption by 51.57%. In fifth we have selected SSTL15_DCI and downscale the power consumption by 49.93%. In sixth experiment we set SSTL18_I_DCI IO standard and consumption minimize by 49.20% in total power. At the end we have mark to be worked with SSTL18_II_DCI which is DCI circuit and found 48.78% reduction in total power consumption.
Keywords: SSTL IO standard, Low Power, Energy Efficient, 28 nm FPGA
Scope of the Article: Renewable Energy Technology