Transistor Sizing of CMOS VLSI Circuits in Deep Submicron Technology
M. Venkata Ramanaiah1, Sudhakar Alluri2, B. Rajendra Naik3, N.S.S. Reddy4
1M. Venkata Ramanaiah, Department of ECE, CMRIT, JNTUH, Hyderabad (Telangana), India.
2Sudhakar Alluri, Department of ECE, CMRIT, JNTUH, Hyderabad (Telangana), India.
3B. Rajendra Naik, Department of ECE, UCE, Osmania University, Hyderabad (Telangana), India.
4N.S.S. Reddy, Department of ECE, VCE, Osmania University, Hyderabad (Telangana), India.
Manuscript received on 04 September 2019 | Revised Manuscript received on 13 September 2019 | Manuscript Published on 26 October 2019 | PP: 15-29 | Volume-8 Issue-11S2 September 2019 | Retrieval Number: K100409811S219/2019©BEIESP | DOI: 10.35940/ijitee.K1004.09811S219
Open Access | Editorial and Publishing Policies | Cite | Mendeley | Indexing and Abstracting
© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open-access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In Very-huge scale reconciliation (VLSI) application zone, postponement and power are the significant variables for any advanced circuits. Its observed that the as CMOS Inverter Transistor Size decreases from 1µm to 120nm, power reduced from 3.331 to 2.644 (µW) and delay reduced from 5.026 to 22.66 (pS). It is observed that the table 4 as 28T Full Adder Circuit Voltage Scale decreases from 5 V to 1 V, Total power reduced from 63150 to 2262 (nW) and delay reduced from 39.93 to 38.52 (nS) in 180nm technology. It is observed that the table 6 as 28T Full Adder Circuit Voltage Scale decreases from 2 V to 0.8 V, Total power reduced from 21.39 to 2.916 (µW) and delay reduced from 4.939 to 4.74 (nS) in 90nm technology. It is observed that the table 8 as 28T Full Adder Circuit Voltage Scale decreases from 1.5 V to 0.7 V, Total power reduced from 8.98 to 1.713 (µW) and delay reduced from 4.963 to 4.581 (nS) in 45nm technology.
Keywords: CMOS Inverter, 28T Full Viper, Low Power, Low Territory, Delay, VLSI.
Scope of the Article: Deep Learning