Design of Fast Efficient Radix-16 Sequential Multiplier
B. Gokul1, M. Padmaja2
1B.Gokul, Electronics and Communication Engineering, V R Siddhartha Engineering College, Vijayawada, India.
2M.Padmaja, Electronics and Communication Engineering, V R Siddhartha Engineering College, Vijayawada, India.
Manuscript received on 04 July 2019 | Revised Manuscript received on 09 July 2019 | Manuscript published on 30 August 2019 | PP: 1173-1177 | Volume-8 Issue-10, August 2019 | Retrieval Number: J91800881019/2019©BEIESP | DOI: 10.35940/ijitee.J9180.0881019
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Multiplication is an important function in computer arithmetic operations. The multiplication process will be done by the shift-and-add sequential multiplication procedure. Radix-16 sequential multiplier design generates the radix-16 partial products as two low (L) and high (H) components. In order to reduce cycle time, Brent-Kung adder and two radix 16 carry-save adders are used to generate radix-16 partial products. The proposed design of radix-16 sequential multiplier is efficient over previous designs and comparison depicts ADP and PDP of existing method are 11.22% and 8.45% than proposed method. However, the Excess area-Delay product and Excess-power-Delay product is also lowered. The design is carried out in Xilinx ISE 14.5 software and cadence tool for simulation and synthesis results. Fast efficient radix-16 sequential multiplier can be used in many digital signal processing applications.
Keywords: Radix-16 Sequential Multiplier, Radix-16 Carry-save Adder, Brent-Kung adder, Excess Area Delay product (EADP), Excess power Delay Product (EPDP).
Scope of the Article: Sequential, Parallel and Distributed Algorithms and Data Structures