A 10-bit 150MS/s Pipelined ADC with 2.5bit Gain Stage for High Frequency Applications
G. Kirubakaran1, D. Dineshkumar2, R. Varun Prakash3
1G. Kirubakaran, Department of Electronics and Communication Engineering, Mepco Schlenk Engineering College, Sivakasi, Tamil Nadu, India.
2D. Dineshkumar, Department of Electronics and Communication Engineering, Mepco Schlenk Engineering College, Sivakasi, Tamil Nadu, India.
3R. Varun Prakash, Department of Electronics and Communication Engineering, Mepco Schlenk Engineering College, Sivakasi, Tamil Nadu, India.
Manuscript received on 02 July 2019 | Revised Manuscript received on 09 July 2019 | Manuscript published on 30 August 2019 | PP: 883-886 | Volume-8 Issue-10, August 2019 | Retrieval Number: J90560881019/2019©BEIESP | DOI: 10.35940/ijitee.J9056.0881019
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper proposes a 10-bit pipelined Analog to Digital Converter (ADC) which incorporates various techniques for lesser power and higher performance. The proposed method reduces the computational burden while comparing to the modified Monte-Carlo (MC) method. Pipelined ADC has N number of stages, it has higher resolution and higher frequency of conversion while comparing to other ADCs. The proposed ADC employs five 2.5bit gain stages; instead of 1.5bit gain stages for high accuracy. This method is implemented in the Tanner Software with the Generic 250nm library at a maximum power supply of 5V. The maximum frequency attained is 150MHz; and the ADC exhibits a SNR of 61.96dB. It also attains a 10bits as effective number of bits at the maximum sampling rate.
Keywords: Evolutionary algorithm, Monte-Carlo (MC), Pipelined ADC, 2.5bit gain stage, 10-bit ADC
Scope of the Article: Frequency Selective Surface