Balanced XOR/XNOR Circuits using CNTFET
Anitha N1, Srividya P2
1Anitha N, Department of Electronics & Communication Engineering, Amruta Institute of Engineering & Management Sciences, Bidadi, Karnataka, India.
2Dr. Srividya P, Department of Electronics & Communication Engineering, R V College of Engineering, Bangalore, India.
Manuscript received on 02 July 2019 | Revised Manuscript received on 09 July 2019 | Manuscript published on 30 August 2019 | PP: 746-751 | Volume-8 Issue-10, August 2019 | Retrieval Number: J88900881019/19©BEIESP | DOI: 10.35940/ijitee.J8890.0881019
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In this work, a standard design methodology in different logic styles using Carbon Nano Tube field effect transistor is proposed to construct Balanced XOR/XNOR circuit. The Proposed methodology is build on different basic cells to optimize area, power dissipation and delay. The circuits for Balanced XOR/XNOR can be designed with selecting a Elementary basic cell including two independent inputs and two complementary outputs. The basic cell is then combined with various correction and optimization techniques to build a perfect XOR/XNOR circuit to avoid weak zero and week one at the output. Simulation results of the proposed circuits shows better performances in terms of delay, power and PDP. The proposed circuits are evaluated using cadence virtouso.
Keywords: CNTFET, Adder Circuits, Balanced XOR/XNOR Circuits, Low Power, Delay, power delay product.
Scope of the Article: Nanometer-Scale Integrated Circuits