Long Channel Keeper based Open Loop Difference Amplifier Domino for Noise Tolerant Low Power OR Gates
Manish Tiwari1, Vijayshri Chaurasia2
1Manish Tiwari, Department of Electronics and Communication, MANIT Bhopal, M.P., India.
2Vijayshri Chaurasia, Department of Electronics and Communication, MANIT Bhopal, M.P., India.
Manuscript received on 12 August 2019 | Revised Manuscript received on 17 August 2019 | Manuscript published on 30 August 2019 | PP: 3331-3340 | Volume-8 Issue-10, August 2019 | Retrieval Number: J12210881019/2019©BEIESP | DOI: 10.35940/ijitee.J1221.0881019
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper proposes an open loop difference amplifier with long channel keeper technique for domino logic circuits implemented as wide fan in OR gate. Currently OR gates suffer from high capacitive loading and delays due to such loading. The proposed design uses single stage of comparison and dual keeper arrangement to generate and hold the output logic state. This technique effectively reduces the high input loading from capacitance and manages the power consumption by switching based on the generated difference voltage. As compared to standard footerless domino SFLD, the proposed design OLDA has shown to reduce power consumption by 42% in 64 bit configuration. It has increased average noise immunity by 2.03 times, while maintaining same speed as compared to SFLD. All simulations are done in CMOS technology with 90nm PTM LP models.
Keywords: Dynamic Logic Circuits, OR Gate Domino, Long Channel Keeper, Low Power Digital VLSI Design.
Scope of the Article: Low-power design