FDTD modeling for Crosstalk Reduction in Coupled RLC Interconnects with Active Shielding
R. Sridevi1, P. Chandra Sekhar2, B.K. Madhavi3, T. Satya Savithri4
1Mrs R.Sridevi, Associate professor in ECE Dept at BVRITH college of Engineering for Women has received B.TECH in ECE from KITS(S) and M.E in VLSI & ESD from O.U.
2Dr. P. Chandra Sekhar, Professor of ECE in University College of Engineering, Osmania University Hyderabad.
3Dr.B.K.Madhavi, professor of ECE in Sridevi Women’s Engineering College, Hyderabad.
4Dr. T. Satya Savithri, Professor in ECE Department of JNTUH College of Engineering, Hyderabad.
Manuscript received on 25 August 2019. | Revised Manuscript received on 03 September 2019. | Manuscript published on 30 September 2019. | PP: 1038-1042 | Volume-8 Issue-11, September 2019. | Retrieval Number: J11000881019/2019©BEIESP | DOI: 10.35940/ijitee.J1100.0981119
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper presents efficient geometry for crosstalk noise and delay reduction using Active shielding in RLC interconnects with resistive drivers .FDTD modeling has been used for proposed geometry and is validated by HSPICE simulations for 32nm global interconnects .From the results it has been verified that the proposed model results and HSPICE simulations differ by 5% . From the outcomes it has been confirmed that the proposed model outcomes and HSPICE outcomes differ by 5% and by using proposed geometry crosstalk noise and delay has come down by 73% and 60% when compared to unshielded line.
Keywords: Crosstalk noise, Delay, Active shielding RLC interconnects, FDTD
Scope of the Article: Cross Layer Design and Optimization