Design and Implementation of Compressor Based 32-Bit Multipliers for MAC Architecture
M. Abheesh Kumar1, A. Sudhakar2, J. Venkata Suman3
1M. Abheesh Kumar, PG Scholar, GMR Institute of Technology, India.
2A. Sudhakar, Associate Professor, Department of Engineering and Communication Engineering, GMRIT, India.
3J. Venkata Suman, Assistant Professor, Department of Engineering and Communication Engineering, GMRIT, Rajam, India.
Manuscript received on 23 June 2019 | Revised Manuscript received on 05 July 2019 | Manuscript published on 30 July 2019 | PP: 2007-2011 | Volume-8 Issue-9, July 2019 | Retrieval Number: I8517078919/19©BEIESP | DOI: 10.35940/ijitee.I8517.078919
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Arithmetic operations play a major role in digital circuit design like adders, multipliers etc. Multiplication is an important fundamental arithmetic operation in high performance systems such as microprocessor and digital signal processors circuits. Implementation of multipliers using compressor circuit over conventional adders will reduce the number of levels of addition, which will in turn reduces the latency of the multiplier. Multiplier module is most likely the essential part of MAC (Multiplier-Accumulator) unit design. Compressor based multipliers in MAC architecture design results high performance. FPGA and ASIC implementations of 4:2 compressor based 32-bit Wallace and Dadda multipliers can be done by using Xilinx Vivado and Cadence CMOS technology tools. These results are compared with other multiplier designs with respect to area, latency and power dissipation.
Keywords: Compressors, Verilog HDL, Cadence CMOS 90nm Technology, Xilinx Vivado, MAC.
Scope of the Article: Network Architectures