Design and Implementation of RNS Filter using Modular-Multipliers
P. Bhargavi1, K. Srinivasa Reddy2, M. Durga Prakash3
1P. Bhargavi, Electronics and Communication Engineering, Vr. Siddhartha Engineering College, Vijayawada (A.P), India.
2K. Srinivasa Reddy, Electronics and Communication Engineering, Vr. Siddhartha Engineering College, Vijayawada (A.P), India.
3M. Durga Prakash, Electronics and Communication Engineering, Vr. Siddhartha Engineering College, Vijayawada (A.P), India.
Manuscript received on 30 June 2019 | Revised Manuscript received on 05 July 2019 | Manuscript published on 30 July 2019 | PP: 1325-1329 | Volume-8 Issue-9, July 2019 | Retrieval Number: I8117078919/19©BEIESP | DOI: 10.35940/ijitee.I8117.078919
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In this paper, an efficient RNS based multiply-accumulate (MAC) unit is proposed to implement residue number system (RNS) based finite impulse response filter (FIR). The proposed MAC (PMAC) approach reduces the number of adders in critical path delay. In this work, a FIR filter with PMAC approach is implemented using structural Verilog HDL language. The United Microelectronics Corporation 90 nm technology library has been used for synthesis. The performance metrics such as area, power and delay are obtained using Cadence RTL compiler. The synthesis results shows that RNS filter with PMAC improves clock frequency and reduces delay and area when compared to conventional MAC (CMAC).To compare the performance of the filters power delay product (PDP) is also considered. The PMAC architecture has improved PDP gain by 30.63% when compared to CMAC.
Keywords: FIR Filter, Residue Number System, Multiply-Accumulate unit.
Scope of the Article: Mechanical Design