HDL Implementation of Five Moduli Residue Number System
Tukur Gupta1, Shamim Akhter2, Anandita Srivastava3, Saurabh Chaturvedi4
1Tukur Gupta, Ph.D. Scholar, Department of Engineering and Communication Engineering, Jaypee Institute of Information Technology, NOIDA, India
2Shamim Akhter, Assistant Professor, Department of Engineering and Communication Engineering, Jaypee Institute of Information Technology, NOIDA, India
3Anandita Srivastava, M. Tech. (Engineering and Communication Engineering), Jaypee Institute of Information Technology, NOIDA, India
4Saurabh Chaturvedi, Assistant Professor, Department of Engineering and Communication Engineering, Jaypee Institute of Information Technology, NOIDA, India
Manuscript received on 27 June 2019 | Revised Manuscript received on 05 July 2019 | Manuscript published on 30 July 2019 | PP: 689-693 | Volume-8 Issue-9, July 2019 | Retrieval Number: I7768078919/19©BEIESP | DOI: 10.35940/ijitee.I7768.078919
Open Access | Ethics and Policies | Cite | Mendeley | Indexing and Abstracting
© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The demand for residue number system (RNS) is increasing day by day because of its high speed and fault tolerant characteristics. RNS encodes a large number into group of small numbers, which consequently increases the overall data processing rate. This paper presents an analysis of the forward converter designed using ripple carry adder (RCA), carry save adder (CSA), and half adder-like (HAL), for the figure of merits area, delay, and power for five moduli set: 2n-1, 2n, 2n+1, 2n+1-1, and 2n-1-1 with the standard cells at 90 nm technology. The designing of different blocks has been done in Verilog-HDL. The area, delay, and power of the implemented circuits are obtained using the Synopsys Design Compiler at 90 nm technology node, while VCS is used for verification. It is observed that the area of the architecture using CSA is less, whereas power utilization and timing behavior are better in HAL.
Index Terms: Carry Save Adder (CSA), Forward Converter, Modular Addition, Modular Multiplication, Residue Number System (RNS),
Scope of the Article: Residue Number System