Low Power Design of 2–4 and 4–16 Line Decoders
Grande NagaJyothi1, Gorantla Anusha2, Kundu Debanjan3
1Grande Naga Jyothi, Department of Micro & Nano Electronics SENSE, VIT, Vellore -632014, Tamil Nadu, India
2Gorantla Anusha, Department of electronics, GCT of Coimbatore, Coimbatore, Tamil Nadu, India.
3Debanjan Kunda, Department of Micro & Nano Electronics SENSE, VIT, Vellore -632014, Tamil Nadu, India.
Manuscript received on 30 June 2019 | Revised Manuscript received on 05 July 2019 | Manuscript published on 30 July 2019 | PP: 1220-1224| Volume-8 Issue-9, July 2019 | Retrieval Number: I7509078919/19©BEIESP | DOI: 10.35940/ijitee.I7509.078919
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Here, we are proposing a novel design of 2:4 decoder and 4:16 decoders which are designed by using line decoder concept. By using proposed design, the area and power consumption of 2:4 decoder and 4:16 decoder can be reduced. In the existing work they have used DVL (Dual Value Logic) and Transmission gate Logic to implement a 14-Transistor 2:4 decoder for minimizing the transistor count. By using 2:4 pre-decoders and post-decoders they implemented 4:16 decoders. Mixed logic is also used for this purpose. Here we have implemented a single 2:4 decoder with minimum transistor count and low power consumption which is used to design a 4:16 decoder. We implement the proposed design in Cadence Virtuoso simulation at 90nm technology and calculated the power and area.
Keywords: Decoder, inverter, mixed logic, Transmission
logic
Scope of the Article: Low-power design