Impact of Band to Band Tunneling on Transient Performance of Dual Gate Tunnel Field Effect Transistor (TFET)
Deepak Kumar1, Raj Gaurav Mishra2, Ranjan Mishra3, Amit Kumar Shrivastava4
1Deepak Kumar, Department of Electrical and Electronics Engineering, University of Petroleum and Energy studies (UPES), Dehradun, India.
2Raj Gaurav Mishra, Department of Electrical and Electronics Engineering, University of Petroleum and Energy studies (UPES), Dehradun, India.
3Ranjan Mishra, Department of Electrical and Electronics Engineering, University of Petroleum and Energy studies (UPES), Dehradun, India.
4Amit Kumar Shrivastava, Research Scholar, Department of Electronics Engineering, Jagan Nath University, Jaipur, India.
Manuscript received on 30 June 2019 | Revised Manuscript received on 05 July 2019 | Manuscript published on 30 July 2019 | PP: 284-288 | Volume-8 Issue-9, July 2019 | Retrieval Number: H7236068819/19©BEIESP | DOI: 10.35940/ijitee.H7236.078919
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Tunnel Field Effect Transistor (TFET) is gated reverse biased P-I-N diode structured semiconductor device and can be considered as a reliable low power device. TCAD (Sentaurus 2D) simulations for various Gate metal work function (4.1-4.3 eV) shows that its ON-current (ION) arises from quantum mechanical band-to-band tunneling (B2BT) and observed that threshold Voltage (VT) for TFET decreases with increase in Gate metal work function. The thermionic emission of electrons in MOSFET limits the sub-threshold swing (SS) by 60 mV/dec whereas TFET has potential for low SS ie. SS<60 mV/dec. TCAD Simulations confirmed that that the Gate – Drain capacitance (Cgd) strongly follows the Gate capacitance (Cgg) all over the voltage range (0-0.9V) which increases the miller capacitance for TFET. It is investigated that for TFET, the injection of carriers into the channel is through B2BT which effectively couples the Gate charge to the Drain. A look up table based Verilog-A model is generated for TFET and used to simulate the static and dynamic behavior of TFET based digital circuit in Cadence spectre. Miller effect causes the peak voltage overshoots are noticed at the drain side during transient responses and can be responsible for dynamic power loss and high turn ON/OFF delay
Index Terms: B2BT, Verilog A, Tunneling, Miller Effect, Gate Capacitances.
Scope of the Article: High Performance Computing