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Low Power and High-Speed Efficient Multiplier Design
M. Saravanan1, R. Arun Sekar2, Ramanan S.V3, M. Srinivasaperumal4

1M. Saravanan, Department of ECE, SNS College of Technology, Coimbatore, Tamil Nadu, India.
2R.Arun Sekar, Department of ECE, GMR Institute of Technology, Rajam, Andhra Pradesh, India.
3Ramanan. S.V, Department of ECE, PPG Institute of Technology, Coimbatore, Tamil Nadu, India.
4M. Srinivasaperumal,. Department of ECE, SNS College of Technology, Coimbatore, Tamil Nadu, India.

Manuscript received on 02 June 2019 | Revised Manuscript received on 10 June 2019 | Manuscript published on 30 June 2019 | PP: 1149-1155 | Volume-8 Issue-8, June 2019 | Retrieval Number: H6601068819/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: This paper centers around the plan of Fixed width multipliers utilizing Baugh-Wooley based corner calculation. The greatest supreme mistake after truncation is ensured to be close to 1 unit of minimum position (ulp), by utilizing the adjusted settled width multiplier plan. Fixed width multiplier is a subset of Fixed width multiplier, registers just n most noteworthy bits for n*n increase. In the traditional strategy cancellation, decrease, truncation and adjusting techniques are considered together with the end goal to limit the quantity of half adders and full adders amid tree decrease. This plans to diminish the most extreme stature of the halfway item exhibit and standard designs. This system is quite compelling in all multiplier outlines, however particularly in the short piece width two’s supplement multipliers for elite installed centers. The Booth based stall calculation is a moderately clear method for doing marked augmentations. The proposed Fixed width Booth based corner multiplier is contrasted and the customary Fixed width marked multiplier got from quantization plot. It has executed in Multiply and Accumulate (MAC) unit and Arithmetic and Logic Unit (ALU) and FIR channels utilizing settled width Booth based corner multiplier. The proposed technique beats existing strategy regarding area and delay.
Keyword: Multiply and Accumulate (MAC), Baugh-Wooley (BW), Booth multiplier, Full adders (FA), Ripple Carry adder (RCA), Fixed width multiplier, signed multiplier.
Scope of the Article: Design Optimization of Structures.