Performance Analysis of Low Power 8-Tap FIR Filter using PFAL
Premananda B.S.1, Ganavi M.G2
1Premananda B.S., Department of Telecommunication Engineering, RV College of Engineering, Bengaluru, India.
2Ganavi M.G., Department of Telecommunication Engineering, RV College of Engineering, Bengaluru, India.
Manuscript received on 02 June 2019 | Revised Manuscript received on 10 June 2019 | Manuscript published on 30 June 2019 | PP: 365-374 | Volume-8 Issue-8, June 2019 | Retrieval Number: H6357068819/19©BEIESP
Open Access | Ethics and Policies | Cite | Mendeley | Indexing and Abstracting
© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Power is the crucial criterion in the systems such as processors, filters and VLSI systems. The increase in the use of portable devices has increased the demand for low power devices. Finite Impulse Response (FIR) filter is one of the basic building blocks of Digital Signal Processor (DSP). FIR filter is the building block of DSP and can be realized by integrating adders, multipliers and delay elements. Adiabatic logic is one of the promising techniques to minimize power dissipation of static CMOS circuits. In this paper, 8-tap direct form-I FIR filter is realized by integrating Square Root Carry Select Adder (SQRT CSLA) using Binary to Excess-1 Converter (BEC), Reduced Complexity Wallace Tree Multiplier (RCWTM) and Barrel shifter. SQRT CSLA overcomes the problem of carry rippling delay in Ripple Carry Adder (RCA). SQRT CSLA using BEC overcomes the problem of power dissipation and area in SQRT CSLA using RCA by replacing equal sized blocks RCA with unequal sized RCA blocks. RCWTM reduces the area and power dissipation in Wallace tree multiplier by replacing compressors with adders. Both static CMOS and Positive Feedback Adiabatic Logic (PFAL) based direct form-I FIR filter are realized in Cadence Virtuoso (180 nm technology) and simulated in Spectre. PFAL based SQRT CSLA using BEC, RCWTM, Barrel shifter and realized 8-tap FIR filter dissipates 75.89 %, 81.03 %, 97.6 %, and 83.4 % less power when compared to static CMOS based circuits.
Keyword: Barrel shifter, CMOS, FIR, PFAL, Square Root Carry Select Adder, Wallace Tree Multiplier.
Scope of the Article: Predictive Analysis