Implementation of Twin Precision-Reduced Computation Modified Booth Multiplier in FPGA
Priya Stalin
Priya Stalin, Associate Professor, Department of Electronics and Communications Engineering, Dr. MGR Educational and Research Institute, Maduravoyal, Chennai, India.
Manuscript received on 10 June 2019 | Revised Manuscript received on 17 June 2019 | Manuscript Published on 19 June 2019 | PP: 649-656 | Volume-8 Issue-8S June 2019 | Retrieval Number: H11110688S19/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open-access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Multipliers can be implemented either in ASIC or FPGA. Comparing FPGAs to ASICs, FPGAs are very flexible. Adding to this, a significant advantage of FPGAs over ASICs is reconfigurability and hardware reusability. FPGA is said to be more advantageous than ASIC multipliers because of its internal optimization algorithms. This research is narrowed down to exploit the advantages of FPGA. Multiplication is a complex process and it is hard to be implemented in hardware environments like ASIC. The process of multiplication consumes more hardware resulting in delay and high power dissipation in ASIC, which is a non-reusable hardware. The complexity in multiplication in ASIC is the problem statement which causes increase in metrics like area, power and delay.
Keywords: The Complexity in Multiplication in ASIC is the Problem Statement Which Causes Increase in Metrics Like Area, Power and Delay..
Scope of the Article: Algorithms and Complexity