Hardware Accelerator Design Approach for CNN-Based Low Power Applications
Govinda Rao Locharla1, Revathi Pogiri2
1Govinda Rao Locharla, Department of ECE, GMR Institute of Technology, Rajam (A.P), India.
2Revathi Pogiri, Department of ECE, Sri Venkateswara College of Engineering, Etcherla (A.P), India.
Manuscript received on 01 May 2019 | Revised Manuscript received on 15 May 2019 | Manuscript published on 30 May 2019 | PP: 2061-2065 | Volume-8 Issue-7, May 2019 | Retrieval Number: G6320058719/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Field Programmable Gate Array (FPGA) based CNN accelerator is getting popular due to its high performance at lower power requirements. Since the convolution process requires the huge number of the multiply and accumulate (MAC) operations it costs more amount of area and power. In this paper, a generalized pipelined architecture for the CNN model is reported and the functionality of the key elements is quantitatively presented. This pipelined architecture employs the limited number of functional units and schedules the operation over the more number of clock cycles. This pipelined approach helps in achieving lesser hardware complexity, therefore, lesser power and area requirements at the cost of speed. The architecture presented in this paper can be customized for given CNN model by configuring Image size, Kernel sizes, Kernel buffer, pooling and activation type, etc. Finally, the hardware requirements of CNN architecture for LeNet-5 is reported as a case study and analyzed.
Keyword: ASIC, CNN, FPGA, GPU, LeNet, MAC.
Scope of the Article: Mobile Computing and Applications.