Approximate Adder: Lower-Part or Adder
K. Varnika
K. Varnika, Department of ECE, G. Narayanamma Institute of Technology and Sciences, India.
Manuscript received on April 20, 2020. | Revised Manuscript received on April 30, 2020. | Manuscript published on May 10, 2020. | PP: 1176-1180 | Volume-9 Issue-7, May 2020. | Retrieval Number: G5832059720/2020©BEIESP | DOI: 10.35940/ijitee.G5832.059720
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: High-performance VLSI systems are essential in real-time applications, in order to increase the performance of the VLSI systems, an approximate computing technique is followed where the performance of the circuit is enhanced by trading off it with a slight loss in the accuracy. These approximate circuits are used in error-tolerant applications, where output need not be accurate. This paper concentrates mainly on approximate adders, as they are major building blocks of DSP systems. The analysis of the Lower-part OR Adder for 4-bit addition and comparison of it with the precise adder i.e., Ripple Carry Adder using the mentor graphics tool in 90 nm CMOS technology are presented in this paper. Our experimental results show that there is 17%-70% savings in power dissipation, 4%-32% saving in the area, and 19%-84% savings in time due to approximate adder. As the LOA-2 and LOA-3 are performing optimally these two adders can be used for error-tolerant applications and based on the requirement LOA-2 or LOA-3 can be selected.
Keywords: Approximate Computing, Approximate Adder, Lower-part OR Adder, VLSI.
Scope of the Article: Computer Architecture and VLSI