An Efficient VLSI Design of 32X32 bit Multiplier using Wallace Tree Algorithm in Vivado HLS and Xilinx ISE Software using VHDL
Sunkana Rama Krishna1, Arun Kishore Voleti2, Jagadeesh Pasumarthi3, Yelusuri Deepika4, Rachakonda Sai Kiran5
1Arun Kishore Voleti, Department of ECE, LIET, Vizianagaram, India.
2Jagadeesh Pasumarthi, Department of ECE, LIET, Vizianagaram, India.
3Deepika Yelusuri, Department of ECE, LIET, Vizianagaram, India.
4Sai Kiran Rachakonda, Department of ECE, LIET, Vizianagaram, India.
5S. Rama Krishna, Associate Professor, Department of ECE, LIET, Vizianagaram, India.
Manuscript received on April 20, 2020. | Revised Manuscript received on April 30, 2020. | Manuscript published on May 10, 2020. | PP: 490-495 | Volume-9 Issue-7, May 2020. | Retrieval Number: G5299059720/2020©BEIESP | DOI: 10.35940/ijitee.G5299.059720
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Multiplier is the most basic component present in any digital system. These multipliers are mainly used in Digital Signal and Image Processing applications. In applications like image detection latest sophisticated algorithms like CNN are used which contains MAC units in their design. The multiplier used in MAC unit requires huge memory, offers high latency and consumes more power. There are many algorithms such as Combinational, Sequential and Array Multiplication Algorithms which helps in designing Multiplier. The major drawback in all designs is circuit complexity. The problem of latency and power dissipation are also present. Considering all the drawbacks present in those algorithms this paper proposes the usage of Wallace Tree Algorithm which consumes less power and has low latency. Also, there are many ways to add the final stage of partial products generated such as Carry Look Ahead adder, Carry Select Adder etc. This paper uses both Carry Select Adder and Ripple Carry Adder for performing final addition of partial products. All previous partial products are added using Half adders and Full adders. The Multiplier is designed using VHDL in Xilinx ISE and Vivado Platform.
Keywords: Carry Select Adder, Multiplier, Ripple Carry Adder, Vivado HLS, Wallace Tree Algorithm, Xilinx ISE.
Scope of the Article: VLSI Algorithms