Analysis of Low Power Dynamic Comparator
M. Sai Navya1, U. Koti Reddy2, N. Yaswanth Kumar3, G. Sai Krishna4, P. Lakshman5
1M. Sai Navya, UG Student, Department of ECE, Koneru Lakshmaiah Education Foundation, Vaddeswaram, A.P , India.
2U. Koti Reddy, UG Student, Department of ECE, Koneru Lakshmaiah Education Foundation, Vaddeswaram, A.P , India.
3N. Yaswanth Kumar, UG Student, Department of ECE, Koneru Lakshmaiah Education Foundation, Vaddeswaram, A.P , India.
4G. Sai Krishna, Associate Professor, Department of ECE, Koneru Lakshmaiah Education Foundation, Vaddeswaram, A.P , India.
5P. Lakshman, Associate Professor, Department of ECE, Koneru Lakshmaiah Education Foundation, Vaddeswaram, A.P , India.
Manuscript received on April 20, 2020. | Revised Manuscript received on May 01, 2020. | Manuscript published on May 10, 2020. | PP: 329-332 | Volume-9 Issue-7, May 2020. | Retrieval Number: G5294059720/2020©BEIESP | DOI: 10.35940/ijitee.G5294.059720
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Low power consumption, high performance dynamic comparators are widely used in high-speed Analog to Digital Converters (ADCs) and advanced input/output circuits. Mostly unique comparators utilize the latching stage thorough cross-coupled inverters, which gives a solid positive feedback, to fasten the comparison and reduce the static- power dissipation. In this paper, the analysis of dynamic comparators having best performance parameters in terms of power dissipation is presented. This is achieved by adopting low power techniques like adding transistors and sizing them to get efficient circuit. The proposed circuits are able to reduce power dissipation from 40-50%.
Keywords: Dynamic Comparators, High performance, Low power, Delay, Analog-to-Digital.
Scope of the Article: High Performance Computing