Comparative Analysis of Efficient Hierarchy Multiplier using Vedic Mathematics
D. Naveen Sai1, Damarla Paradhasaradhi2, R.S. Ernest Ravindran3
1D. Naveen Sai, Department of Electronics and Communication, Koneru Lakshmaiah Education Foundation, Guntur (Andhra Pradesh), India.
2Damarla Paradhasaradhi, Department of Electronics and Communication, Koneru Lakshmaiah Education Foundation, Vijayawada (Andhra Pradesh), India.
3Dr. R.S. Ernest Ravindran, Department of Electronics and Communication, Koneru Lakshmaiah Education Foundation, Vijayawada (Andhra Pradesh), India.
Manuscript received on 01 May 2019 | Revised Manuscript received on 15 May 2019 | Manuscript published on 30 May 2019 | PP: 1374-1378 | Volume-8 Issue-7, May 2019 | Retrieval Number: G5129058719/19©BEIESP
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Abstract: Hierarchy multiplication is desirable since of its capacity to carry the multiplications with high speed. An approach of implementation of hierarchy multiplier involves utilization of array multiplier. A drawback of array multiplier is that it has a critical delay path. In order to overcome this problem, a new methodology has been proposed in this paper which replaces the array multiplier with a Vedic multiplier. In Vedic multiplier ‘Urdhava-tiryakbhyam’ sutra makes the partial products and erase the unnecessary multiplication steps. The methodology has been implemented in mentor graphics tool using 45nm technology. From the simulation results, the proposed methodology reduces the area and delay when compare to the different existing designs
Keyword: Vedic Multiplication, Array Multiplication, Carry Save Adder, Hierarchy Multiplier.
Scope of the Article: Predictive Analysis.