Highly Secure and Fast AES Algorithm Implementation on FPGA with 256 Bit Key Size
Amrik Singh1, Yoginder Talwar2, Ajay Prasad3
1Amrik Singh, Department of Electrical Communication & Electronics Engineering, Guru Tegh Bahadur Institute of Technology, GGSIP University, (New Delhi), India.
2Dr. Yoginder Talwar, Scientist, National Informatics Centre, (New Delhi), India.
3Dr. Ajay Prasad, Professor, Department of Information Technology, University, Petroleum and Energy Studies, Dehradun (Uttarakhand), India.
Manuscript received on 15 December 2016 | Revised Manuscript received on 21 December 2016 | Manuscript Published on 30 December 2016 | PP: 1-8 | Volume-6 Issue-7, December 2016 | Retrieval Number: G2398126712/16©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The Block cipher AES is a symmetric key cryptographic standard used for transferring block of data in secure manner for server based communication networks, SCADA systems for Oil refinery, Oil and Gas Pipe Lines, and Smart Grids based applications. High level security of data transfer needs long key size i.e. 256 bits, analysis of certain ideas of round key expansion mechanisms from given key data are discussed and the same is implemented in FPGA configuration with 128 bits and 256 bits key size to achieve low latency, high throughput with high security.
Keywords: Advance Encryption Standard, Encryption, Decryption, FPGA, VHDL, Virtex-5.
Scope of the Article: Algorithm Engineering