An Efficient Design of R-2R Digital to Analog Converter with Better Performance Parameter in (90nm) 0.09-µm CMOS Process
Anuradha S. Kherde1, Pritesh R. Gumble2
1A.S. Kherde, Department of Electronics & Telecommunication, Sipna’s College of Engineering & Technology, (Maharashtra), India.
2Prof. P.R. Ghumble, Department of Electronics & Telecommunication, Sipna’s College of Engineering & Technology, (Maharashtra), India.
Manuscript received on 8 December 2013 | Revised Manuscript received on 18 December 2013 | Manuscript Published on 30 December 2013 | PP: 24-27 | Volume-3 Issue-7, December 2013 | Retrieval Number: G1377123713/13©BEIESP
Open Access | Editorial and Publishing Policies | Cite | Mendeley | Indexing and Abstracting
© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: CMOS technology favors digital circuitry but imposes a challenge to the analog designer faced with limitations such as process gradients and random device variations. With increasing complexity comes an increase in the number of devices in a system, and hence, an increase in the die size required for that system. As the die space available becomes more and more critical, the need to optimize each function in the system for area consumption. The DAC is optimized for large integrated circuit systems where possibly dozens of such DAC would be employed for the purpose of digitally controlled analog circuit calibration. An R-2R Ladder is a simple and inexpensive way to perform digital – to – analog conversion by using repetitive arrangements of precision resistor networks in a ladder-like configuration. The application of Microwind 3.1 for realizing R2R DAC bridges the gap between theory and the real circuit. This paper provides a detailed view of a 4 bit R2R ladder with optimum accuracy by using Microwind 3.1.This paper describes the design of a DAC which is of contemporary nature with reasonable speed, resolution and linearity with lower power, low area. This paper provides a detailed view of a 4 bit DAC with optimum accuracy by using Microwind 3.1. For all about Pre Layout simulation has been realized using 90 nm (0.09um) CMOS process Technology.
Keywords: Digital-To-Analog Converters (DAC),R-2R, DNL, INL, Etc.
Scope of the Article: Measurement & Performance Analysis