Power Optimization of High Speed Pipelined 8B/10B Encoder
Gajendra Singh Solanki1, Rekha Agarwal2, Sandhya Sharma3
1Gajendra Singh Solanki, Departemnt of Electronics and Communication, Suresh Gyan Vihar University, Jaipur (Rajasthan), India.
2Rekha Agarwal, Departemnt of Electronics and Communication, Suresh Gyan Vihar University, Jaipur (Rajasthan),
3Shandhya Sharma, Departemnt of Electronics and Communication, Suresh Gyan Vihar University, Jaipur (Rajasthan),
Manuscript received on 8 December 2013 | Revised Manuscript received on 18 December 2013 | Manuscript Published on 30 December 2013 | PP: 14-16 | Volume-3 Issue-7, December 2013 | Retrieval Number: G1362123713/13©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In this paper a modified 8B/10B Encoder is designed. Power consumption of 8B/10B encoder is reduced by deactivating unwanted switching of the clock. The clock signals are great source of power dissipation. Clock signal is not use to perform any digital computation. it is mainly used for synchronization of sequential circuits. Hence clock signal don’t carry any information. So, clock-gating techniques can be used to save power by reducing unnecessary clock activities inside the gate module.
Keywords: Clock Gating, Pipelining, 8B/10B Encoder.
Scope of the Article: Discrete Optimization