Sub-50nm Tri-layered Strained Si/SiGe/Si Channel nMOSFET
Lalthanpuii Khiangte1, Rudra Sankar Dhar2
1Lalthanpuii Khiangte, Department of Electronics and Communication Engineering, National Institute of Technology, Mizoram, Aizawl, India.
2Rudra Sankar Dhar, Department of Electronics and Communication Engineering, National Institute of Technology, Mizoram, Aizawl, India.
Manuscript received on 04 April 2019 | Revised Manuscript received on 11 April 2019 | Manuscript Published on 26 April 2019 | PP: 361-364 | Volume-8 Issue-6S April 2019 | Retrieval Number: F61310486S19/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open-access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Development of a sub-50nm MOSFET on incorporating two strained silicon layers in the channel region has been carried out leading to the advent of 50nm and 100nm channel length devices. Further scalability and device analysis have been due, which has been now the focus of this paper. The effects of strained Silicon-Germanium thickness on the device leakage current have been analyzed and optimized using Synopsis TCAD simulations. The enriched device characteristics for the scaled 30nm device have also been examined in comparison to 40nm and 50nm channel length device MOSFET.
Keywords: Double Strained Si Layers, Quantum Vonfinement, SHOI, Nanoscale Regime, sMOSFET.
Scope of the Article: Communication