Design and Analysis of Power Efficient Single-Phase Clocking Master Slave Flip-flops for Sequential Circuits
P. Sreelakshmi1, K. Hari Kishore2, E. Raghuveera3, KVKVL Pawan Kumar4, Fazal Noor Basha5
1P. Sreelakshmi, P G Student, Department of Electronics & Communication Engineering, Deemed University, Guntur, Andhra Pradesh, India.
2K. Hari Kishore, Professor, Department of Electronics & Communication Engineering, Deemed University, Guntur, Andhra Pradesh, India.
3E. Raghuveera, Assistant Professor, Department of Electronics & Communication Engineering, Deemed University, Guntur, Andhra Pradesh, India.
4KVKVL Pawan Kumar, Assistant Professor, Department of Electronics & Communication Engineering, Deemed University, Guntur, Andhra Pradesh, India.
5Fazal Noor Basha, Assistant Professor, Department of Electronics & Communication Engineering, Deemed University, Guntur, Andhra Pradesh, India.
Manuscript received on 04 April 2019 | Revised Manuscript received on 11 April 2019 | Manuscript Published on 26 April 2019 | PP: 184-189 | Volume-8 Issue-6S April 2019 | Retrieval Number: F60490486S19/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open-access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The basic element in sequential circuit design is flip-flop and flip-flops are widely used in memories. This paper outlines the design of Single-Phase Clocking flip-flop using various methods like pass transistor and the transmission gate logic. The main scope of this paper is to design a flip-flop with optimized power. The optimization of power and the reduction in transistor count is achieved by using transmission gates and pass transistor logic. 45nm CMOS based design technology chosen for the implementation technology. The performance metrics of Flip-flop designs were compared with different sequential circuits using transmission gate and pass transistor logic techniques. Pre-layout analysis results indicated that, proposed designs excelled in optimizing the average power. When compared with the other designs, the proposed flip-flop is designed using only 11- transistors and the average power consumption of the proposed flip-flop is bring downed to 108.9 nW. All the designs are simulated and verified with PYXIS tool running on 3.41 GHz processor. These flip-flop designs are best suited for low power and high performance applications.
Keywords: Transmission Gate, Flip-flop, Low Power, Single Phase Clocking (SPC).
Scope of the Article: Communication