A Low Power 8-Bit Current-Steering DAC Using CMOS Technology
P.Ramakrishna1, M. Nagarani2, K. Hari Kishore3
1P.Ramakrishna, Research Scholar, Department of Electronics and Communications Engineering, Koneru Lakshmaiah Educational Foundation, Vaddeswaram, Guntur, Andhra Pradesh, India.
2M. Nagarani, Professor, Department of Electronics and Communications Engineering, Koneru Lakshmaiah Educational Foundation, Vaddeswaram, Guntur, Andhra Pradesh, India, Anurag Group of Institutions, Hyderabad, India.
3K Hari Kishore, Professor, Department of Electronics and Communications Engineering, Koneru Lakshmaiah Education Foundation, Vaddeswaram, Guntur, Andhra Pradesh, India.
Manuscript received on 04 April 2019 | Revised Manuscript received on 11 April 2019 | Manuscript Published on 26 April 2019 | PP: 137-140 | Volume-8 Issue-6S April 2019 | Retrieval Number: F60390486S19/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open-access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Design of 8-bit current-steering DAC is proposed in this paper. The800 MHz conversion rate has been obtained by a fully custom designed new architecture. With the operating voltage of 1V and 180nm CMOS technology this DAC is designed. The power dissipation is of 42.92uw which is very low. The DAC will thus create a “stair stepping” analog output until digital input is met or the voltage supply is reached. The measured integral non linearity (INL) is less than ±0.31LSB and the static differential non-linearity error (DNL) is ±0.418 LSB.
Keywords: DAC, Current Steering, Current Mirror, Cascade.
Scope of the Article: Communication