Performance Analysis of 6Transistor Single bit Adder Element
K. V. K. V. L Pavan Kumar1, G L Sravanthi2, N. Suresh Kumar3, V. S. V Prabhakar4
1K.V.K.V.L Pavan Kumar, Assistant Professor, Department of Electronics & Communication Engineering, Koneru Lakshmaiah Educational Foundation, Vaddeswaram, Guntur (Andhra Pradesh), India.
2G.L Sravanthi, Assistant Professor, Department of Computer Science & Engineering, Vignan’s Nirula Institute of Technology & Science for Women, Guntur (Andhra Pradesh), India.
3N.Suresh Kumar, Assistant Professor, Department of Electronics & Communication Engineering, Koneru Lakshmaiah Educational Foundation, Vaddeswaram, Guntur (Andhra Pradesh), India.
4V.S.V Prabhakar, CISCO Chair, International Institute of Digital Technologies, Tirupati (Andhra Pradesh), India.
Manuscript received on 07 April 2019 | Revised Manuscript received on 20 April 2019 | Manuscript published on 30 April 2019 | PP: 1677-1681 | Volume-8 Issue-6, April 2019 | Retrieval Number: F5056048619/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper encloses a 2T MUX to reduce the transistor count in single bit adder element to 6. It uses HEP-1 tool in MENTOR GRAPHICS to compare parameters like Power, delay, PDP, and ADP with 8TEXOR, 8TMUX, 6T adder etc. with 1.2V supply voltage in 130-nm technology. The proposed one presents an improvement of 51%, 98% in ADP and PDP respectively when compared to the 8T MUX based Single bit adder element. Further, it emphasizes low power dissipation and minimum delay required to exhibit the desired logic that is useful in many portable applications.
Keyword: Single Bit Adder Element, 8TMUX, 2TMUX, MUX Area Delay Product (ADP), Power Delay Product (PDP
Scope of the Article: Measurement & Performance Analysis