Design and Evaluation of Cubic Torus Network-on-Chip Architecture
Akash Punhani1, Neetu Faujdar2, Sunil Kumar3
1Akash Punhani, Department of Computer Science and Engineering, Amity University, ASET, Noida, (Uttar Pradesh), India.
2Neetu Faujdar, Department of Computer Science and Engineering, Amity University, ASET, Noida (Uttar Pradesh), India.
3Sunil Kumar, Department of Computer Science and Engineering, Amity University, ASET, Noida (Uttar Pradesh), India.
Manuscript received on 07 April 2019 | Revised Manuscript received on 20 April 2019 | Manuscript published on 30 April 2019 | PP: 1672-1676 | Volume-8 Issue-6, April 2019 | Retrieval Number: F4090048619/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The network on chip is the key component of the achieving the high performance required by the system designed on the single chip. The mesh and torus topologies have found there places in various system on chips. Still there is an exploration for the better topologies, which can help in reducing the latency of the packet delivered from one core to another core on the chip. In this paper, a new variant of Torus topology has been proposed and the performance of the network is being evaluated on simulator using various synthetic traffics. On comparing the average latency of the cubic torus with other five topologies, it has been observed that the cubic torus has the least latency in comparison to the other existing topologies.
Keyword: Topology, Network on Chip, Interconnection Networks.
Scope of the Article: Networked-Driven Multicourse Chips