Design of Low Power Encoder Using Different MOS Techniques for a 4-bit Flash ADC
Feroz Mohammad1, B. Chandrasekhar2, V. Devikapriya3, T. NavyaSree4
1Mr. Feroz Mohammad, Assistant Professor, Department of ECE, Koneru Lakshmiah Educational Foundation, Institution Deemed to be University, Vaddeswaram, Guntur (A.P), India.
2B. Chandrasekhar, Department of ECE, Koneru Lakshmiah Educational Foundation, Institution Deemed to be University, Vaddeswaram, Guntur (A.P), India.
3V. Devika Priya, Department of ECE, Koneru Lakshmiah Educational Foundation, Institution Deemed to be University, Vaddeswaram, Guntur (A.P), India.
4T. NavyaSree, Department of ECE, Koneru Lakshmiah Educational Foundation, Institution Deemed to be University, Vaddeswaram, Guntur (A.P), India.
Manuscript received on 07 April 2019 | Revised Manuscript received on 20 April 2019 | Manuscript published on 30 April 2019 | PP: 1410-1414 | Volume-8 Issue-6, April 2019 | Retrieval Number: F392901048619/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Among all architectures, Flash ADCs are most preferred ones. The main reason for selecting Flash ADC is due to its high speed of operation. The two important building blocks for the Flash ADC are Comparator and Encoder. In this paper a mux based encoder with resolution 4 is proposed and implemented using CMOS, Pass Transistors and Transmission Gate logic. Simulation results shows that encoder with Transmission Gate logic has less delay compared to Encoder with CMOS Logic. Simulation is carried out with Mentor Graphics tool with a supply voltage of 1.2 V using 130nm technology.
Keyword: Flash ADC, Encoder, Transmission Gate, CMOS.
Scope of the Article: Low-power design