Performance Analysis of Low Power Dual Edge Triggered Flip Flop using Power Gating Techniques
Karthikeyan S1, Ramamoorthy K2, Chelladurai T3
1Karthikeyan.S, Department of ECE, PSNA College of Engineering, and Technology, Dindigul (Tamil Nadu), India.
2Ramamoorthy.K, Department of ECE, PSNA College of Engineering, and Technology, Dindigul (Tamil Nadu), India.
3Chelladurai.T, Department of ECE, PSNA College of Engineering, and Technology, Dindigul (Tamil Nadu), India.
Manuscript received on 07 April 2019 | Revised Manuscript received on 20 April 2019 | Manuscript published on 30 April 2019 | PP: 819-825 | Volume-8 Issue-6, April 2019 | Retrieval Number: F3740048619/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Dual Edge Triggered flip flop is a sequential element that works on both positive (rising) as well as negative (falling) edges of clock signal. This flip flop exhibits some unique behavior which reduces leakage power when Muller C element is used to design the circuit. Hence five novel designs of DET are obtained by using sleep signals that bears some resemblance to common latch-mux DET flip flop but differs on operation. Along with these new DET design, such as Latch-Mux DET flip flop, True Single Phased DET flip flop, Conditional Precharge DET flip flop and Latch-Mux design that uses C element (for the function of multiplexer) are considered here. Performances of these designs are improved in the proposed method by using power gating technique. Power Gating is a technique which is used in the circuit to deliver the power, only when the circuit is in active mode. Power Gating Techniques such as Sleep Transistor logic and Lector stack are employed separately in the circuit. The former method uses sleep signals while effective stacking of transistors is incorporated in latter one in order to reduce the leakage power in the circuit. Performance analysis is carried out using TANNER simulation software tool.
Keyword: C Element, Dual Edge Triggered (DET) Flip Flop, Lector Stack,Power Gating Technique, Sleep Transistor Logic.
Scope of the Article: Low-power design