VLSI Implementation of LICI Cipher
Nigar Ayesha1, Bibhudendra Acharya2
1Nigar Ayesha, Department of Electronics and Telecommunications Engineering, National Institute of Technology Raipur, Raipur (Chattisgarh), India.
2BibhudendraAcharya, Department of Electronics and Telecommunications Engineering, National Institute of Technology Raipur, Raipur (Chattisgarh), India.
Manuscript received on 07 April 2019 | Revised Manuscript received on 20 April 2019 | Manuscript published on 30 April 2019 | PP: 1184-1191 | Volume-8 Issue-6, April 2019 | Retrieval Number: F3737048619/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: With the rise in tiny computing devices communicating end-to-end, followed the demand to reinforce security while not compromising on the constraints like area, power, memory, performance, latency etc. Lightweight cryptography is ideal for satisfying security requirements in resource constraint devices. LiCi is one of the recent lightweight ciphers with moderate emphasis on security for low-area overhead and low-power applications. In this paper, three different hardware architectures for this lightweight algorithm are proposed. The architectural strategies include a serialized architecture, a reduced datapath architecture and a pipelined architecture. The serial architecture consists of serially performing the operations with fewer resources using a control circuit targeting low-area and power at the expense of increased latency and low performance. The reduced datapath architecture targets a reduction in the width of the input bits for low-area and low-power with tradeoffs in security due to memory-based key-scheduling. The pipelined architecture targets high performance and throughput by reducing the critical path delay with the inclusion of registers at appropriate intervals. The proposed hardware designs target Xilinx FPGA platforms like Spartan 3, Virtex 4 and Virtex 6. The synthesis and implementation of the designs for Post Place and Route is done in Verilog using Xilinx ISE 14.6. The simulations for the same are observed in ISim Simulator. The power consumption is estimated using XPower analyzer. A fair comparison is performed with the existing ciphers in terms of slices occupied, latency, throughput and dynamic power for the targeted FPGA platforms. The dynamic power consumption of the proposed architectures is compared with the previous results for a clock frequency of 10 MHz for Virtex 6 FPGA. Among the three designs, reduced datapath design consumes the least dynamic power followed by the serial architecture.The pipelined architecture occupies higher power due to the increase of registers and clock transitions.
Keyword: LiCi Cipher, IoT, RFID Tags, Feistel Network, Security, Lightweight Cryptography, FPGA, Verilog, Slices.
Scope of the Article: VLSI Algorithms