1.5mW,14.68V/µS-Low Power and High Speed Comparator Design for ADC Applications
Shashidhar K1, Chaithanya Mannepalli2, Sreenivasa Rao Ijjada3
1Shashidhar. K, Research Scholar, Department of Electronics and Communication Engineering, Gandhi Institute of Technology and Management University, Visakhapatnam, Andhra Pradesh, India.
2Chaithanya Mannepalli, Research Scholar, Department of Electronics and Communication Engineering, Gandhi Institute of Technology and Management University, Visakhapatnam, Andhra Pradesh, India.
3Sreenivasa Rao Ijjada, Assistant Professor, Department of Electronics and Communication Engineering, Gandhi Institute of Technology and Management University, Visakhapatnam, Andhra Pradesh, India.
Manuscript received on 13 April 2019 | Revised Manuscript received on 20 April 2019 | Manuscript Published on 26 July 2019 | PP: 1322-1326 | Volume-8 Issue-6S4 April 2019 | Retrieval Number: F12680486S419/19©BEIESP | DOI: 10.35940/ijitee.F1268.0486S419
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open-access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Advanced medical equipments embedded with the sensors, analog to digital converters (ADC) and other equipment. Gain amplifier and the comparator are key blocks in ADCs improvement. Comparator is the key element in achieving a low offset and high slew ratein the ADCs, in addition power and speed optimizationdesigns are preferred. To achieve high speed and low power a modified architecture of a comparator is introduced. A 5V two stage comparator is designed to meet the specifications as, offset value <8.4mV, power dissipation <1.5mW and slew rate>14.68V/µS. Cadence Virtuoso tools and SCL 0.18 µm technology parameters are used for design. Designed comparator shows improved slew rate and power consumption in comparison with the existing comparators.
Keywords: Comparator, High Speed, ADC, low Offset, High Slew Rate.
Scope of the Article: Communication