Analysis and Optimization of timing paths in MTCMOS based Change-Sensing Flip Flop for SoC Design
Bhargavi N.S1, Shylashree N2
1Bhargavi N.S, Department of Electronics and Communications Engineering, R V College of Engineering, Bengaluru, Karnataka, India.
2Shylashree N, Department of Electronics and Communications Engineering, R V College of Engineering, Bengaluru, Karnataka, India.
Manuscript received on 10 April 2019 | Revised Manuscript received on 17 April 2019 | Manuscript Published on 24 May 2019 | PP: 774-780 | Volume-8 Issue-6S3 April 2019 | Retrieval Number: F11530486S319/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open-access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: VLSI industry is very vast and fast-growing industry in the world with increasing complexity and intensive development. In semiconductor industry there is always a trade of between area, power and timing. As there are advancements in the technology along with miniaturization taking place the timing and power play important role for SoC chip designing and production. The main aim in the SoC chip design is to make a cost-effective chip with low area, power consumption with efficient and fast timing response. By using latest technological advancement techniques and methods the exact timing can be maintained. By proper analysis of the timing paths, and suitable optimization techniques we can have accurate timing and reduce power consumption. In this paper, Change-Sensing flip flop is designed to have accurate timing and minimum power consumption. The tool used is Cadence virtuoso with 45nm technology and MTCMOS technology is used for power reduction. Results verify that the designed Change-Sensing flip flop with MTCMOS technology consumes very less power with-respect to many flip-flops designed for the industry. The designed FF reduces power consumption by 44.37 % when compared to TGFF. The FF has setup time of 47.70 pS and hold time of -15.15 pS. The designed flip flop will help in overall power reduction in the SoC chip design and will improve the timing response.
Keywords: Setup and Hold Time Measurement, MTCMOS Technique, low Power, Single-Phase Clock, flip-flop (FF).
Scope of the Article: Communications