Design and Implementation of High Performance and Low Power Mixed Logic Line Decoders
Chandra Sekhar Savalam1, Korapati Prasanti2, A.S.Haranath3
1Chandra Sekhar Savalam, Department of Electronics and Communication Engineering, Dhanekula Institute of Engineering and Technology, Vijayawada, Andhra Pradesh, India.
2Korapati Prasanti, Department of Electronics and Instrumentation Engineering, VR Siddhartha Engineering College, Vijayawada, Andhra Pradesh, India.
3A.S.Haranath, Department of Electronics and Communication Engineering, Dhanekula Institute of Engineering and Technology, Vijayawada, Andhra Pradesh, India.
Manuscript received on 08 April 2019 | Revised Manuscript received on 15 April 2019 | Manuscript Published on 26 July 2019 | PP: 635-640 | Volume-8 Issue-6S4 April 2019 | Retrieval Number: F11310486S419/19©BEIESP | DOI: 10.35940/ijitee.F1131.0486S419
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open-access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The decoders are widely used in the logical circuits, data transfer circuits and analog to digital conversions. A mixed logic design methods for the line decoders are used to combining the transmission gate logic, pass transistor logic, and complementary metal-oxide semiconductor (CMOS) technology provides desired operation and performance. A novel topology is presented for the 2 to 4 decoder requires a fourteen transistor topology aiming on reducing the transistor count and operating power and a fifteen transistor topology aiming on high power and low delay performance. The standard and inverting decoders are designed in each of the case, gives a total of four new designs circuits. All the proposed decoders have compact transistor count compared to their conservative CMOS technologies. Finally, a variety of proposed designs present a noteworthy improvement in operating power and propagation delay, outperforming CMOS in almost all the cases.
Keywords: Decoders, Mixed Logic Design, Power and Delay Optimization.
Scope of the Article: Communication