Investigation of Junction-less Double Gate MOSFET With High-k Gate-oxide and Metal Gate Layers
Ambika1, Gaurav Dhiman2
1Ambika, Department of Electronics and Communication Engineering, Mody University, Lakshmangarh, India.
2Dr. Gaurav Dhiman, Department of Electronics and Communication Engineering, Mody University, Lakshmangarh, India. Mody University, Lakshmangarh, India.
Manuscript received on 05 April 2019 | Revised Manuscript received on 14 April 2019 | Manuscript Published on 24 May 2019 | PP: 289-292 | Volume-8 Issue-6S3 April 2019 | Retrieval Number: F10590486S319/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open-access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: With the development of Moore’s law, the size of the transistors is decreasing so fast which led to various effects like leakage current and short channel effects(DIBL, low threshold voltage etc). With the scaling, the performance of device degrades, so to improve the performance of the device multi-gate architectures can be used. It improves the control of gate over channel increases and it also provides ideal sub-threshold swing and better ION/IOFF ratio. Generally, SiO2 is used as oxide material in metal oxide semiconductor field effect transistors (MOSFET) but it leads to high leakage current and direct tunneling of electrons. So in this paper to overcome all these problems SiO2 is replaced by high-k dielectric materials (HfO2, Al2O3, ZrO2). High-k materials provide high density and low energy consumption. In this paper, the study of n-type JL-DG MOSFET with high-k dielectric oxide materials and all results were compared with SiO2 material layer.
Keywords: DIBL, JL-DG MOSFET, SCEs, etc.
Scope of the Article: Communication