A Low Power and High Reliability Magnetic Full Adder Circuit Design Based on Separated Pre-Charge Sensing Amplifier
K.Sudhakar1, S.Arunprathap2
1K. Sudhakar, Assistant Professor, Department of Electronics and Communication Engineering, M. Kumarasamy College of Engineering, Karur (TamilNadu), India.
2S. Arunprathap, Assistant Professor, Department of Electronics and Communication Engineering, M. Kumarasamy College of Engineering, Karur (TamilNadu), India.
Manuscript received on 05 April 2019 | Revised Manuscript received on 14 April 2019 | Manuscript Published on 24 May 2019 | PP: 189-192 | Volume-8 Issue-6S3 April 2019 | Retrieval Number: F10370486S319/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open-access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The Magnetic Tunnel Junction is entrenched in CMOS to built nonvolatile memory and logic circuits. Nevertheless this kind of circuit grievesfrom low reliability in sensingprocess and memoryelement. This leads torestriction of its real-worldapplication for logic operations. This project work helpsa noveldesign of magnetic full adder toavoid the above problemby using separated pre-charge sensing amplifier circuit. The proposed method results in operation at a lower supply voltage, less than one volt by separatedischarging and evaluationphases of the sensing operation. Higher sensing reliability is achieved by reducing the effect of process variation. When compared to previous methods it preserves speed and low power consumption. This work all the circuits are designed by post layout simulation tool.
Keywords: Magnetic Full Adder, CMOS, MTJ and SPCSA.
Scope of the Article: Communication