Design of Efficient Single Precision Floating Point Multiplier using Urdhva Triyagbhyam Sutra of Vedic Mathematics
Sai Venkatramana Prasada G S1, G Seshikala2, Niranjana S3
1Sai Venkatramana Prasada G S, Assistant Professor, Research Scholar, Department of Electronics & Communications, Srinivas University, Mangaluru, Reva University, Bangalore, India.
2Dr. G Seshikala, Professor, Department of Electronics & Communications, Reva University, Bangalore, India.
3Dr. Niranjana S, Associate Professor Senior Scale, Manipal Institute of Technology, Manipal Academy of Higher Education, Manipal, Udupi, India.
Manuscript received on 05 April 2019 | Revised Manuscript received on 14 April 2019 | Manuscript Published on 24 May 2019 | PP: 160-162 | Volume-8 Issue-6S3 April 2019 | Retrieval Number: F10290486S319/19©BEIESP
Open Access | Editorial and Publishing Policies | Cite | Mendeley | Indexing and Abstracting
© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open-access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Multiplication of floating point(FP) numbers is greatly significant in many DSP applications. The performance of the DSP’s is substantially decided by the speed of the multipliers used. This paper proposes the design and implementation of IEEE 754 standard single precision FP multiplier using Verilog, synthesized and simulated in Xilinx ISE10.1. Urdhva Triyagbhyam Sutra of Vedic mathematics is used for the unsigned mantissa calculation. The design implements floating point multiplication with sign bit and exponent calculations. The proposed design is achieved high speed with minimum delay of 3.997ns.
Keywords: Floating Point Numbers, Single Precision, IEEE 754, Urdhva Triyagbhyam Sutra, Vedic Mathematics.
Scope of the Article: Communications