Design of Efficient Approximate Compressor for Digital Image Processing
Marimuthu. R1, Elsie Rezinold2, Mayank Rathi3
1Marimuthu R, School of Electrical Engineering, Vellore Institute of Technology, Vellore, India.
2Elsie Rezinold, School of Electrical Engineering, Vellore Institute of Technology, Vellore, India.
3Mayank Rathi, School of Electrical Engineering, Vellore Institute of Technology, Vellore, India.
Manuscript received on 05 March 2019 | Revised Manuscript received on 17 March 2019 | Manuscript Published on 22 March 2019 | PP: 341-345 | Volume-8 Issue-5S April 2019 | Retrieval Number: ES3439018319/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open-access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: For various error tolerant applications like multimedia and signal processing, approximate computing is the most suited computing technique. With the cost of accuracy, approximate computing gives us faster and efficient results with possibly low power consumption. A new approach and design towards optimizing the partial products reduction stage of a compressor-based multiplier have been introduced in this paper. Two new designs of 4:2 compressors and six new designs of approximate multipliers using the approximate compressors have been proposed. The results of the simulation of the proposed designs show that there has been a significant improvement in the accuracy with reduction in power and time consumption when we compare to the previous approximate designs. An image processing application is used to prove the efficiency of the proposed designs.
Keywords: Approximate Compressors, Digital Image Processing, Edge Detection.
Scope of the Article: Computer Architecture and VLSI