Design a Low Power and High Speed 130nm Fulladder using Exclusive-OR and Exclusive-NOR Gates
Soniya Nuthalapati1, P.V. Sai Ranjitha2, Kalapala Radhika Rani3, Lingisetty Lourdu SasiRekha4, Sirisha Mekala5, Firdosia Parveen Mohammad6
1Soniya Nuthalapati*, E.C.E, JNTUK, Guntur, India.
2P.V.Sai Ranjitha, E.C.E, JNTUK, Guntur, India.
3Kalapala Radhika Rani, E.C.E, JNTUK, Guntur, India.
4Lingisetty Lourdu Sasi Rekha, E.C.E, JNTUK, Guntur, India.
5Sirisha Mekala, E.C.E, JNTUK, Guntur, India.
6Firdosia Parveen Mohammad, E.C.E, JNTUK, Guntur, India.
Manuscript received on March 12, 2021. | Revised Manuscript received on March 19, 2021. | Manuscript published on March 30, 2021. | PP: 81-86 | Volume-10 Issue-5, March 2021 | Retrieval Number: 100.1/ijitee.E86590310521| DOI: 10.35940/ijitee.E8659.0310521
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This literature illustrates the high speed and low power Full Adder (FADD) designs. This study relates to the composited structure of FADD design composed in one unit. In this the EXCL-OR/EXCL-NOR designs are used to design the FADD. Mostly concentrates on high speed standard FADD structure by combining the EXCL-OR/EXCL-NOR design in single unit. We implemented two composite structures of FADD through the full swing EXCL-OR/EXCL-NOR designs. And the EXCL-OR/EXCL-NOR design is done through pass transistor logic (PTL) and the same design projected on the composited FADD design. Such that the delay, area of the design, power requirement for the circuit gets optimized. The two composited FADD designs are compared and reduced the constraints of power requirement, area, delay and the power delay product (PDP). The simulated outcomes are verified through 130nnm CMOS mentor graphics tool.
Keywords: Full Adder (FADD), EXCL-OR EXCL-NOR, Pass transistor logic (PTL), Mentor graphics tool.