Design of Combinational Logic Circuits Using Memristor and CMOS Logic
Kichchannagari Omkar Reddy1, D. Gracin2, V. Ravi3, S. Ananiah Durai4
1Kichchannagari Omkar Reddy, Department of Electronics Engineering, Vellore Institute Technology VIT, Chennai (Tamil Nadu), India.
2D.Gracin, Department of Electronics Engineering, Vellore Institute Technology, VIT University VIT, Chennai (Tamil Nadu), India.
3V.Ravi, Department of Electronics Engineering, Vellore Institute Technology VIT, Chennai (Tamil Nadu), India.
4S.Ananiah Durai, Department of Electronics Engineering, Vellore Institute Technology VIT, Chennai (Tamil Nadu), India.
Manuscript received on 07 March 2019 | Revised Manuscript received on 20 March 2019 | Manuscript published on 30 March 2019 | PP: 167-173 | Volume-8 Issue-5, March 2019 | Retrieval Number: E2930238519/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Introduction of the memristor has paved the way to many inventions in VLSI domain. The properties of memristor such as the nanometer scale measurements and its non-volatile memory qualities have yielded more attention towards research people. The nanometer scale highlight of the memristor makes another door open for the realization of innovative circuits for logic blocks from the more standard designs. Non-volatile memory property empowers us to acknowledge new outline strategies for an assortment of computational components that prompt novel models. By this, there comes the idea of the combination of the Nano-scale memristor and CMOS, which ends up conceivable to diminish usage of silicon territory accordingly giving a promising alternative in the plan of memristor and CMOS based circuits. In this paper, we are presenting a combinational circuit design using memristor and CMOS logic as well as the implementation of a built-in self-test circuit to test the core functionalities of the logic. It is composed of a test pattern generator and output response analyzer which will compare the output response of the unit under test circuit with the pre-stored expected patterns of the unit under test. Designing the circuit utilizing this mix advantage of memristor and CMOS spares a great deal of chip space and power utilization and it is reliable as well.
Keyword: CMOS, Memristor, BIST, LFSR.
Scope of the Article: Nanometer-Scale Integrated Circuits