Urdhva Tiryak Sutra Based Ancient Multiplication in Reversible Logic Circuits
K. Saranya1, N. Priya2, M. Priyadharshini3, D. Vedhanivetha4, B. Lukman5
1Mrs. K. Saranya, Assistant Professor, Department of EEE, Dr. Mahalingam College of Engineering & Technology, Pollachi, Tamil Nadu. India.
2Ms. N. Priya, PG Scholar, Department of Applied Electronics, Dr. Mahalingam College of Engineering & Technology, Pollachi, Tamil Nadu, India.
3Ms. M. Priyadharshini, UG Scholar, Department of Electrical and Electronics Engineering, Dr. Mahalingam College of Engineering & Technology, Pollachi, Tamil Nadu, India.
4Ms. D. Vedhanivetha, UG Scholar, Department of Electrical and Electronics Engineering, Dr. Mahalingam College of Engineering & Technology, Pollachi, Tamil Nadu, India.
5Mr. B. Lukman, UG Scholar, Department of Electrical and Electronics Engineering, Dr. Mahalingam College of Engineering & Technology, Pollachi, Tamil Nadu, India.
Manuscript received on February 10, 2020. | Revised Manuscript received on February 22, 2020. | Manuscript published on March 10, 2020. | PP: 685-697 | Volume-9 Issue-5, March 2020. | Retrieval Number: E2130039520/2020©BEIESP | DOI: 10.35940/ijitee.E2130.039520
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The proposed work analyses the employment of an ancient mathematical approach for building an arithmetic logic unit. Dissipation of power is one of the major driving issues in VLSI design. With the assistance of reversible gates, the power dissipation and loss of information can be minimized. The speed and accuracy of the Arithmetic Logic Unit depends on the propagator. Employing the traditional mathematics sutras technique within the computation algorithm reduces the complexity, duration and power. Due to the effect of environmental factors on the digital circuits, parity conserving technique is incorporated for providing error detection ability. The proposed work deal with the design and analysis of 32 bit reversible multiplier using ancient sutras with and without parity conserving technique .The planned work is implemented on Xilinx ISE Spartan 6E series of FPGA and simulation results are obtained. By using Cadence EDA tool, power, area and delay are calculated. The quantum parameters are calculated manually for 32-bit reversible multiplier using ancient technique with and without parity conserving technique using Urdhva Tiryakbhyam sutra.
Keywords: Ancient Multiplier, ASIC Parameters, Parity Conserving, Quantum Parameters
Scope of the Article: Digital System and Logic Design